TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41
0-output line (fig. 8-5) and a negative output at the 1-
dc voltage applied to the VCO. This higher dc voltage
output line. The positive output at the 0-output line is
increases the VCO, causing the bit-timing signal from
fed back to the set (S) input steering circuit, where the
FFC-22 to occur sooner, and moving its transitions
next positive timing pulse (A, fig. 5-9) sets FFD-2, thus a
closer to the 90 phase-lock condition. Thus, the
negative pulse was provided (M, fig. 5-9) from the 1-
generated clock signals from the VCO are adjusted
output line of FFD-2; this pulse advances the receive
automatically so that its output frequency, applied
clock. The positive output of FFD-1 (fig. 8-5), applied to
through BAUD RATE switch 1A1S2 to the 128 divider-A
FFD-3, clears FFD-3, providing a negative output at the
module, is always exactly 128 times the input bit-timing
1output line (M, fig. 5-9). The positive output at the 0-
signal frequency.
output line, fed back to the input steering circuit, allows
the next positive timing pulse (A, fig. 5-9) to set FFD-3
5-21. Receive Timing
therefore, a negative pulse appeared at the 1-output line
of FFD-3. This pulse retards the receive clock.
a. Add-Subtract Control Logic. Clock signals, at
(2) Assuming that the receive clock is early
128 times the baud rate as selected by BAUD RATE
(timing signal transitions occur sooner than the data-
switch 1A1S2 (fig. 8-5), are applied through inverter IN-
transitions), bistable FFD-1 (fig. 8-5) provides a positive
22 (128 divider-A module) to inverter IN-23 in the add-
output (L, fig. 5-9) as described in (1) above. This
subtract logic module. The timing signals are inverted,
positive output clears bistable FFD-3 (fig. 8-5), which
and the positive transitions (A, fig. 5-9) are applied to
provides a negative output pulse (N, fig. 5-9) as
bistable FFG-1, in the 128 divider-B module (fig. 8-5).
described in (1) above. With the output of bistable FFC-
Bistable FFG-1 divides the input frequency by 2 (B, fig.
27 supplying an early timing transition (P, fig. 5-9), no
coincidence is possible between the positive output of
bistable FFD-5, through AND gates GAS-5 though GAS-
FFC-27 and the inverted data signal (J, fig. 5-9). As a
6 (b below). Bistables FFC-23 through FFC-27 (fig. 8-5)
result, bistable FFD-2 is never cleared and its 1 output
form the remainder of the seven-stage countdown chain
remains in a set or positive condition, so that no
(D, through H, fig. 5-9), providing an output timing signal
negative pulse is produced to advance the receive
equal to the baud rate (bit-time). To minimize distortion
timing clock.
of the received data signal (due to a phase difference
b. Clock Correction. Correction of the receive
between the transmit timing and the receive timing), the
clock is accomplished in the 128 divider-B module. The
receive timing clock is synchronized with the data clock,
1-output from bistable FFD-3 (fig. 8-5) in the add-
by comparing the receive bit-timing output from bistable
subtract control logic module is applied to AND gates
FFC-27 with the received data transitions.
GAD-6 and GAD-7 which require two positive inputs to
(1) Assuming that the receive clock is late
be enabled and provide a positive output. With the
(timing signal transitions occur later than the receive
FFD-3 output line 1 in a positive condition (N, fig. 5-9),
data transitions), the positive data-bit (K, fig. 5-9) allows
AND gates GAD-6 or GAD-7 can be enabled, depending
the 128 times baud timing signal to set bistable FFD-1
on the state of bistable FFG-1. Assuming bistable FFG-
clear side (fig. 8-5), providing a negative output from
1 (fig. 8-5) is in a set state; the 1-output line is positive
FFD-1 (L, fig. 5-9). This negative output has no effect
and the 0-output line is negative. The negative output
on subsequent circuitry. When the inverted data signal
of the 0-output line inhibits AND gate GAD-6 providing a
(J, fig. 5-9) is applied to the clear input steering AND
negative input to the C input steering circuit; the positive
circuit of bistable FFD-1 (fig. 8-5), the positive timing
output at the 1-output line enables GAD-7 which
trigger (A, fig. 5-9) produces a positive output from the
provides a positive input to the S-input steering circuit.
clear side of FFD-1 (L, fig. 5-9) that is applied to the
Under these conditions. the next positive clock timing
clear (C input of bistable FFD-2 (fig. 8-5) and FFD3.
signal from inverter IN-23, in the add-subtract control
With the positive output of FFC-27 (H, fig. 5-9) in
coincidence with the positive output of FFD-1 (L, fig. 5-
9). FFD-2 is cleared providing a positive output at the
Change 5
5-21
