TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41
noise signals from affecting the MD-674(P)/G when the
RATE switch 1A1S2 is applied to inverter IN-22 and
external timing signal is removed.
then to a seven-stage binary counter (bistables FFC-16
through FFC-22) that divides the selected input
(2) The VCO provides a bit-timing signal from
frequency by 128, providing an output timing signal
the 128 divider-A module, 90 out of phase with the
equal to the operating bit-rate. Inverter IN-22 assures
incoming bit-timing signal. In this case, the VCO
proper phasing of the input signal to bistable FFC-16.
frequency is phase locked to a frequency that provides a
The set (1) output of bistable FFC-22 is applied through
clock signal (to the 128 divider-A module) exactly 128
connector XA5, pin J, to risetime and falltime shaper No.
times the incoming bit-timing signal.
If the VCO
2 in the dual output polar drivers module. The output of
frequency is not correct, its frequency is appropriately
risetime and falltime shaper No. 2, which provides sharp
adjusted by OR gates GOA-4 and GOA-5 and AND gate
leading and trailing edges of the timing signal, is applied
GAI-4 (which together make up an exclusive OR circuit).
to polar driver amplifiers PDA-3 and PDA-4. Each
(3) Assuming the in-phase condition, the
amplifier provides a square wave, polar output bit-timing
input bit-timing signal is applied to differential amplifier
signal to the transmitting equipment. The two outputs,
DIA-2, providing two outputs (A and B, fig. 5-8). The
in phase with one another, accommodate external
generated bit-timing signal from the 0 output of FFC-22
transmitting equipments that require either phase (strap
selectable) of bit-timing signals.
an output from differential amplifier DIA-2 (A, fig. 5-8),
b. External Clock.
produces a negative output from GOA-4 (E, fig. 5-8)
(1) The external clock timing signal is applied
whenever the two inputs (A and C, fig. 5-8) are negative
to the modem at a bit-rate, which is incompatible with
and in coincidence. Output of GOA-5 is also negative
the timing requirements of the MD-674(P)/G. Since the
whenever its two inputs (B and D, fig. 5-8) are negative
timing circuits require a clock signal of exactly 128 times
and in coincidence. Output of GOA-4 and GOA-5 are
the bit-rate, an internal variable-control oscillator (VCO)
applied to AND gate GAI-4 which required two positive
is used to generate the necessary clock signals of 153.6
inputs (E and F, fig. 5-8) to provide a negative output.
kc. A phase lock loop automatically adjusts the output
The resultant output from GAI-4 (G, fig. 5-8) is twice the
frequency of the VCO to exactly 128 times the operating
bit-rate and is symmetrical, resulting in a constant
rate of the applied bit-timing signal. The VCO frequency
average dc voltage that is applied to maintain the VCO
(approximately 153.6 kc) is applied to the 128 divider-A
frequency in phase.
module through BAUD RATE switch 1A1S2 as
(a) If the VCO were not in phase with
described in a above. Two outputs, 180 out of phase
the input timing signal, the output of FFC-22 (C, fig. 5-8)
with one another, at the selected bit-rate are applied to
in the 128 divider-A module (bit-timing) would not be
OR gates GOA-4 and GOA-5. The second input to OR
exactly 90 out of phase with the input timing signal.
gates GOA-4 and GOA-5 is externally applied at a bit-
Waveforms H and J, figure 5-8, indicate a generated bit-
rate equal to the clock signal. The external timing
timing signal that is early with respect to the input bit-
signals are fed to differential amplifier DIA-2, which
timing signal (A and B, fig. 5-8). Because of the
produces two output signals 1800 out of phase with each
coincidence required by GOA-4, GOA-5, and GAI-4
other. Differential amplifier DIA-2 also prevents any
(described above), the output of GAI-4 (M, fig. 5-8) is no
longer symmetrical, resulting in application of a lower
5-19
