TM 11-5805-424-15/NAVELEX 0967-220-9010/TO 31W2-2G-41
(approximately 0 volt), which is applied to the post
b. Risetime and Falltime Shaper. Timing signals
detection filter circuits in receive discriminator filter FL3.
are applied to amplifier Q1 of risetime and falltime
e. The post detection circuits remove the doubled
shaper No. 1 through a biasing network (resistors R1,
R2, and R3). A 6-volt level input causes transistor Q1 to
carrier frequency and apply the changing dc voltage
conduct, and a ground level input cuts off transistor Q1.
(positive for mark, and negative for space) to differential
The output square wave from transistor Q1 varies
amplifier NSA-1 (Q17 and Q18.), where the other input
between ground and -15 volts. Resistor R4 is the
is a reference from BIAS ADJ resistor 1A1R13. The
collector limiting resistor, and resistor R5 is the collector
sinusoidal recovered data applied to transistor Q17 is
load resistor for transistor Q1 and the emitter coupling
also coupled to the emitter of Q18 through emitter
resistor to transistor Q2. Transistors Q2 and Q3 form a
resistor R60. As the input voltage of transistor Q17
grounded-base,
complementary
symmetry
polar
becomes more positive (above ground), the inverted
amplifier. With transistor Q1 conducting, ground is
output also increases (more negative) while, at the
applied to cut off transistor Q2, allowing capacitor (,5 to
same time. the output of transistor Q18 becomes more
charge to approximately +6 volts through conducting
positive (due to increased reverse bias on transistor
transistor Q3. With transistor Q1 cut off, the -15 volts
Q18). Since both outputs are applied simultaneously to
applied to transistor Q2 emitter biases transistor Q2 into
the 6-volt clamp circuit, the net effect is a constant
conduction. Capacitor C, discharges and then charges
positive output level during the mark bit. When the
to approximately -6 volts through transistor Q2. Since
input signal through transistor Q17 becomes more
transistor Q2 and Q3 each present the same high
negative (below ground),the inverted output becomes
impedance to the charging of capacitor C5, the voltage
more positive; at the same time, the output of transistor
across capacitor C5 is almost a perfect ramp, ranging
Q18 becomes less positive, thereby, maintaining the
linearly from +6 to -6 volts, in approximately the 27
output at a constant negative level during the space
microseconds required by the external equipments to
input bit. Thus, NSA-1 converts the sinusoidal input
which the timing signals are applied. Resistor R6 is the
data signal to a square wave output data signal.
emitter dropping resistor for transistor Q3. Transistor
Resistors R57 and R58 are the collector load resistors.
Q4 amplifies the input signal and applies it to linear
Diodes CR15 and CR16 prevent the collector voltage
amplifiers PDA-: 3 and PDA-4. Resistor R7 is the
from going higher than +6 volts.
collector load resistor, and diode CR2 clamps the
f. The output signal levels from amplifier NSA-1
collector of transistor Q4 to -6 volts when transistor Q4
are applied, through the external connector, to 6-volt
is cut off.
clamp transistor Q19. Diodes CR17 and CR18 maintain
c. Amplifier PDA-3. Amplifiers PDA-3 and PDA4
the output level between ground and -6 volts,
are identical circuits; therefore, only amplifier PI)A-, is
respectively. Resistor R62 is the 6-volt dropping resistor
described in detail.
Amplifier PDA-3 consists of
when transistor Q19 conducts, resistor R6.3 is a
constant-current source amplifier Q6
and
current-
collector load resistor, and resistors R64 and R65 form a
switching amplifier Q5, connected in a common-base
voltage divider to set the operating voltage for BIAS
configuration for maximum gain and minimum
ADJ resistor 1A1R13.
distortion.
Transistor Q5 is essentially an emitter
follower the output of which follows the input signal;
5-17 Dual Output Polar Driver Circuits
transistor Q6 is the emitter load for transistor Q5. Since
the two transistors are in series, their common current
varies as the input signal applied to transistor Q5 varies.
a. General. The timing output polar driver circuits
The action of the two transistors provides
consist of two identical groups of shaping and amplifying
circuits. Risetime and falltime shaper No. 1 and linear
amplifiers PDA-1 and PDA-2 provide corrected receive
output timing signals; risetime and falltime shaper No. 2
and linear amplifiers PDA-3 and PDA-4 provide
uncorrected transmit timing output signals. Only the
first group of circuits is described in detail below.
Change 5
5-16
