TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41
cycle (128 actual inputs) of the bit-timing signal, until the
logic module clear bistable FFG-1.
The resultant
bit-timing transition from bistable FFC-27 is in line
positive output at the 0-output line now enables AND
(synchronized) with the data transition.
gate GAD-7, while the negative output at the 1-output
line inhibits AND gate GAD-6; thus the S-input steering
(2) Assuming that bistable FFC-27 output bit-
circuit passes the next positive clock timing pulse to
timing signal is late (H, fig. 5-9), one clock pulse is
reset bistable FFG-1. Bistable FFG-1 is alternately set
prevented from triggering bistable FFG-1 (fig. 8-5) as
and reset by successive positive transitions of the clock
described in (1) above; as a result, one count is lost in
signal, thus providing a 2-to-1 signal division. The 1-
the timing chain, thereby retarding the receive clock by
output of bistable FFG-1 is applied to AND gates GAS-5
one count. However, with an early output from bistable
and GAS-6, which act as the steering inputs to bistable
FFC-27, a negative output is provided by bistable FFD-2
FFD-5. The positive-going transitions of bistable FFG-1
(a (1 above) which is applied to AND gates GAS-4 and
output line 1 (B, fig. 5-9) are alternately applied through
GAS-7. Depending on the state of bistable FFD-5, one
AND gates GAS-5 and GAS-6 thus alternately setting
of these gates is enabled at the trailing edge (positive
and resetting bistable FFD-5 by successive positive-
transition) of the bistable FFD-2 output, providing a
going transitions from bistable FFG-1. The output of
positive pulse to trigger bistable FFD-5. Triggering the
bistable FFD-5 is applied to bistable FFC-23 and
second bistable in a counting chain advances the
subsequently to the remainder of the seven-stage
counting sequence by two (since two inputs from the
countdown chain, resulting in an output (from bistable
first bistable in the counting chain are normally
FFC-27) that is equal to the bit-time.
required). Because one clock pulse is inhibited from
(1) Assuming that bistable FFC-27 output bit-
bistable FFG-1 at the same time that bistable FFD-5 is
timing signal is early (P, fig. 5-9), the negative output
triggered, the net effect is to advance the overall count
produced by bistable FFD-3 (fig. 8-5) inhibits both AND
by one, thus decreasing the time required to trigger
gates GAD-6 and GAD-7. The resulting negative output
bistable FFC-27 and moving the bit-timing transition (H,
from each gate inhibits both input steering circuits to
bistable FFG-1. Thus, the next positive clock pulse
transition (J, fig. 5-9).
cannot trigger bistable FFG-1, so the bistable remains in
(3) A count is always subtracted from the
the same state for two clock counts. As a result, the
receive clock once each cycle; therefore, the bit-timing
time required to trigger bistable FFC-27, which provides
signal from bistable FFC-27 at synchronism is
the negative output transition (P, fig. 5-9), is lengthened
alternately late and early by one count, resulting in a 2-
by one count. In this case, 129 input counts, rather than
count jitter. This amount of jitter has a negligible effect
128, are required to trigger bistable FFC27; therefore,
on the overall timing of the data signal. The corrected
the bit-timing transition from bistable FFC-27 is made to
receive bit-timing signal from bistable FFC-27 (fig.
move toward the data transition (J, fig. 5-9). This action
continues, with one clock pulse being deleted for each
Change 5
5-22
