TM 11-5805-424-15/NAVELEX 0967-220-9010/TO 31W2-2G-41
b. When a talk-request signal (1.5-second loss of
the data output signal (strap option); it is also
applied to external receiving equipment that
carrier) is received by the low speed modem receive
require a phase-corrected, bit-timing signal.
circuits, the loss-of-carrier-alarm sensor activates the
talk-request receive circuits.
The latter therefore
provides an inhibit voltage to the loss-of-carrier-alarm
5-5. Order-Wire Circuits
sensor, preventing an alarm indication (due to loss-of-
carrier). Output of the talk-request receive circuits is
also applied to the retiming option select circuits, where
a. When the TALK REQUEST pushbutton is
the retiming of the received data may be switched in or
depressed, the talk-request send circuits apply a 1.5-
out automatically if desired (strap option). The talk-
second inhibit voltage to the send circuit binary divider.
request receive circuit also applies a ground to light the
With the binary divider inhibited for 1.5 second, the data
TALK REQUEST indicator lamp.
Teletypewriter
output terminals remain in a steady mark condition,
transmitting equipment is jacked-in through the ORDER
which will be interpreted at the other station as a talk-
WIRE SEND jack and receiving equipment is jacked-in
request signal (b below). The 1.5-second inhibit voltage
to the ORDER WIRE RECEIVE jack. Operation with
also inhibits the loss-of-carrier alarm, preventing an
teletypewriter data is the same as that for normal data,
alarm indication as a result of loss-of-the-carrier signal
as described in paragraphs 5-2 and 5-3.
(such loss being caused by the inhibit placed on the
binary divider).
Section II. CIRCUIT ANALYSIS
logic diagram (fig. 8-5) is basically the same. The
5-6. General
reference designations for the logic symbols differ to
indicate how the bistable is triggered. The lines on the
a. Because many MD-674(P)/G stages are similar,
left side of the logic symbol represent the inputs; the
and in some cases identical (except for reference
lines on the right side represent the outputs. The upper
designations and component values), a circuit analysis
lines (left and right) of the logic symbol are associated
of each individual stage is not provided in this technical
with one transistor in the stage, and the lower lines are
manual. Instead, a circuit analysis of digital circuit types
associated with the other transistor of the stage.
(with associated logic symbol and pertinent waveforms)
is presented in this section, a circuit analysis of all
analog circuitry used in the equipment is presented in
(1) General. Resistors Re and Rf establish initial
section III, and a complete logic-block diagram analysis
bias for transistors Qa and Qb, respectively.
is provided in section IV.
Resistors Rc and Rd provide the necessary
cross-coupling to allow the stage to change
b. Reference designations such as Ca, Rc, and Qa,
state. The output (180 out of phase with each
used with the circuit descriptions in this section (figs. 5-1
other) are developed across the collector and
emitter of the transistors, with resistors Ra, and
analysis.
To determine the correct reference
designations for a part associated with a particular
CRa and CRb clamp the output voltage to -6
stage, refer to the applicable schematic diagram (figs. 8-
volts when either transistor is cut off.
6 through 8-27). Reference designations such as FF-,
GAI-, and GOI- (figs. 5-1 through 5-7) are arbitrarily
(2) Triggering. To be triggered, the stage shown in
assigned to the logic symbols for the logic analysis
A, figure 5-1, requires positive input pulses.
(section IV).
Resistor Rg, capacitor Ca, and diode CRc form a
differentiating AND gate. With a positive level
c. For detailed analysis of logic circuits described
applied
in section IV, refer to TM 11490.
5-7. Bistable Multivibrator Stages
a. General.
The function of each bistable
multivibrator stage is basically the same and the logic
symbol shown directly under each and used with the
5-3
