TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41
transmitting and receiving equipment and for the timing
frequencies are passed by the receive filter to the
bistable in the MD-674(P)/G receive circuits, to provide
second input amplifier, which shapes the input signals.
an undistorted, phased-corrected output data signal.
The demodulator circuit converts the fsk signals to
Internal timing signals may be supplied by an internal
binary data marks and spaces, at a constant signal
1.2288-mega-cycle (mc) clock oscillator or by an
level. that are applied to the timing bistable. The timing
externally applied bit-timing input signal.
bistable, in conjunction with the timing circuits (para 5-4
below), supplies a retimed and reshaped (regenerated)
data signal to the output driver for application to the
divided by 8, in a three-stage binary divider, and is
external receiving equipment.
applied to the clock option straps. If externally applied,
b. Receive Alarms.
the bit-timing signal activates the variable-control
oscillator and thus provides timing signals to the clock
(1) If the input fsk signals are lost, or fall
option straps.
below a predetermined level as determined by the REC
b. Whichever timing is used, a 153.6-kc signal is
CARRIER ALARM THRESHOLD controls, the second
input amplifier applies an alarm-voltage level to the
applied through the clock option straps to another three-
loss-of-carrier-alarm sensor, activating the 2-second
stage binary divider which, in conjunction with the BAUD
delay. If the alarm condition persists for at least 2
RATE switch, provides a timing signal frequency at 128
seconds, the 2-second delay output causes the common
times the desired bit-rate. The selected 128 times bit-
alarm circuitry to provide a ground that lights the
timing signal is applied from the BAUD RATE switch to
ALARM indicator lamp. Restoration of the input data
the divide-by-128 countdown chain and to add-subtract
removes the activating signal from the 2-second delay,
correction logic.
which removes the ground from the ALARM lamp,
(1) A 7-stage binary counter, the divide-
extinguishing the lamp.
by128 countdown chain, divides the input frequency by
(2) If the recovered data signal is lost in the
128. Countdown chain output provides bit-.timing to the
receive circuits and no transitions are applied to the
output drivers, which supply an uncorrected bit-timing
output driver, the timing bistable remains in a reset
signal to the external data transmitting equipment.
condition due to timing circuit inputs, applying a
(2) Add-subtract correction logic recovers
constant voltage level to the no-transition alarm sensor.
received timing from the received input signal,
This sensor interprets the constant voltage level as an
comparing the resulting generated timing signal
alarm condition and applies an activating vto the 5-
transitions with the received data transitions from the
second delay output activates the common alarm
demodulator circuits; therefore, this logic controls the
circuitry, thereby providing a ground to cause the
counting operation of the second divide-by-128
ALARM lamp to he lighted.
The 5-second delay
countdown chain; it adds timing pulses to the chain if the
contains a control (TRANSITION ALARM TIME
generated timing signal is too slow, and it subtracts
RECEIVE) for fine adjustment of the delay circuits.
timing pulses if the generated timing signal is too fast.
When the data transitions are restored, the activating
By this corrective action, the bit-timing signal output of
voltage is removed from the 5-second delay,
the divide-by-128 countdown chain is kept in phase
extinguishing the ALARM lamp.
(synchronized with the received data. The corrected bit-
timing signal may be used by the timing bistable to
5-4 Timing Circuits
regenerate and retime
These circuits supply bit-timing signals for the external
Change 3
5-2
