TM 11-5820-803-12
c. The operation of a differential decoder is
and RECEIVE ERROR CODING switches in the
appropriate positions.
Operation with an installed
illustrated in B, figure 2-6 which shows the same encoded
external error correcting coder/decoder (KY-801/GSC) is
output sequence developed in A. If a transition occurs
selectable by the same switches. If an external
between bit periods, a ONE is produced at the output. If
coder/decoder is required, it should be installed near the
no transition occurs between bit periods, a ZERO is
PSK modem such that the intermediate cabling does not
produced. The decoder output sequence is identical to
exceed 10 feet in length. The interconnect wiring should
the encoder input shown in A, figure 2-6.
use 75 ohm balanced lines (such as RG-108A/U) for
d. The operation of a differential decoder is
best results. All external coder/decoder signals interface
illustrated in C, figure 2-6 with the encoded output
via one multipin rear panel connector, J6. Further
sequence of A inverted. Again, transitions are decoded
information on the coder/decoder interface is included in
as One's and no transitions as Zero's. The decoder
output sequence is identical to the encoder input shown
receivers manufactured by Texas Instruments, part
in A, figure 2-6.
numbers SN75107 and SN75109. The interface signal
e. The following considerations apply to the use of
data/clock phase relationships are shown in figure 2-8.
differential coding:
All input and output clock lines may be inverted by setting
(1) Differential coding is generally required, as
the appropriate internal switch (para 2-20d).
the PSK modulation technique inherently produces a
d. The internal and external coders are similar in
ONE/ZERO ambiguity over the link.
that they produce two output symbols for each input data
(2) Differential coding does not affect the
bit. Therefore, when error-correcting coding is used, the
symbol rate or the modulation spectrum for random data.
symbol rate transmitted over the link is twice the data
(3) The differential coding/decoding controls,
rate to and from the digital user.
which are located behind the PSK modem front panel,
e. As shown in figure 2-7, the baseband conditioner
must be placed in the ON position to run the modem
in the PSK modem transmitter operates directly on the
self-test. The operator's task will be simplified if these
data from the digital user. The modem transmitter
controls are also normally in the ON position during
INPUT DATA RATE selection switches must always be
operation. Therefore, use of the internal differential
set to the digital user's data rate.
coder and decoder in the PSK modem is advantageous
f. The baseband conditioner in the PSK modem
even though the external coder/decoder or the digital
receiver operates on the symbols transmitted over the
user may be capable of providing the same function.
communications link. Therefore, the setting of the
SYMBOL RATE switches for the PSK modem receiver
2-6.
Coding/Decoding Implementation
depends upon whether error-correcting coding is used in
a. Operational signal paths of the PSK modem with
the link. If no error-correcting coding is used, the
the associated coders and decoders is illustrated in
SYMBOL RATE switches are set to match the digital
user's data rate. If either internal or external error-
selection of the coding and decoding modes of
correcting coding is used, the SYMBOL RATE switches
operation. These switches are tabulated below:
must be set to twice the digital user's data rate.
Switch
Selection
2-7.
Digital User Interface
(Transmit) DIFF ENCODE
ON or OFF
The PSK modem transmitter (fig. 2-9) accepts digital
TRANSMIT ERROR
INTERNAL, NONE, or
inputs for subsequent modulation from any one of
several sources: 1) a line-of-sight (LOS) microwave link,
CODING
EXTERNAL
2) a shielded cable, or 3) a direct MIL-STD-188 user
(Receive) DIFF DECODE
ON or OFF
interface.
The PSK modem receiver provides
RECEIVE ERROR CODING
INTERNAL, NONE, or
compatible digital output capabilities. The PSK modem
EXTERNAL
additionally provides an internally generated clock output
b. The DIFF ENCODE and DIFF DECODE
at a rate equal to the setting of the INPUT DATA RATE
switches are normally placed in the ON position, unless
switches. All digital user interface signals, with the
ambiguity resolution is provided by either the digital user
or an external coder/decoder.
c. Operation with either the internal error-correcting
coding or no error-correcting coding is accomplished by
setting the front panel TRANSMIT
2-8
