TM 11-7021-202-12
g. Bus Utilization. Floating-point arithmetic instructions involve both the CPU and
FPU for their execution. The CPU may determine the status of the FPU by retrieving the
FPU status word on the MEMOUT bus, The status may be changed by the CPU and sent to
t h e FPU on the MEMIN bus. While the memory buses are being used in this fashion,
memory reference cycles are inhibited. If the CPU needs to provide the operands, they are
transferred to the FPU on the MEMIN bus. If memory is to provide one or both operands,
they are obtained from memory on the MEMOUT bus and transferred to the FPU, in which
case the CPU and not the FPU provides the memory address. If the result is required by the
CPU, it is transferred from the FPU on the MEMOUT bus. If the result is to be stored in
memory, the memory address (MEMIN) is supplied by the CPU and the result is supplied by
the FPU (MEMIN). The actual instruction is transferred directly from the CPU to the FPU on
dedicated instruction lines, as are control signals. Note that the FPU does not have direct
access to memory. Memory addresses required during a floating-point arithmetic operation
are provided by the CPU and not the FPU.
In terms of Output operations (I/O), the 16 bidirectional data lines of the I/O bus can be
considered as an extension of MEMOUT in the one direction. During Input operations,
MEMIN can likewise be considered as an extension of the 16 data lines in the opposite
d i r e c t i o n , taking into account proper interfacing in both directions.
In programmed I/O operation (Output), the CPU sends commands, control functions, and
data to the device through the I/O bus and I/O interface. In the case of data transfers, the
CPU first reads the data from memory into an accumulator, then transfers the data from
the accumulator to the I/O interface. In Input operations, the CPU receives data and
status information from the device through the I/O interface and I/O bus in response to a
previously issued command. Data or status information is read into an accumulator, and
in the case of data transferred to memory, from the particular accumulator. Status
information is processed by the CPU to determine what course of action to take,
a c c o r d i n g to the device service routine.
Before an actual DMA operation can take place, the subject device is given the starting
address of a memory data buffer (to or from which data is to be transferred), the number
of words or bytes to be transferred, and finally the operational command. This takes
place in identical fashion to programmed I/O, according to the particular service routine.
The information is obtained from memory by the CPU (MEMOUT) and sent from the CPU
to the device through the I/O bus and I/O interface. Once the DMA operation commences,
memory addresses are supplied by the device and appear on MEMIN. The direction of
data flow depends on the operation being performed. For example: when a write
command is issued to a magnetic tape unit (MTU), data is read from memory as though
there were a direct path from memory (MEMOUT) to the MTU. When a read command is
issued, data is read from the tape and written into memory (MEMIN), again as though
there were a direct data path. Note that the l/O device supplies the memory address by
u s i n g increments of the start address.
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