TM
11-5835-243-34/EE641-AA-MMl-010/E154
MTT/TO
31S3-4-110-1
going edge from the zero-crossing detector
c. J-K Flip-Flop. Line receiver AR7 drives the
(waveforms 6 and 7, fig. 2-4).
J-K flip-flop U8 synchronously with the WR
i. NODE Signal. The output of the full-wave
STROBE signal from the interface. Waveform 3
converted to NRZ1 format by toggling the flip-flop
is a part of the OR gate made up of CR7, CR8 and
on each binary '1'. Write reset is accomplished by
CR9. When the output pulses from the rectifier
driving the reset line (RD) of flip-flop U8. This state
section in each of the three data channels are
places the write current in the proper polarity for
summed together at the outputs of diodes CR7, CR8
Inter-Record Gap (IRG) and Cyclic Redundancy
and CR9, the resulting signal (waveform 8, fig. 2-4)
Check (CRC) character generation (fig. 2-6). The
is the NODE signal. The NODE signal is routed to
synchronized and converted signal is then fed to the
the control logic circuit card (A4) where it is used to
gated head-current driver.
generate RD CLK (read clock). RD CLK is returned
d. Gated Head-Current Driver. Inverter/buffer
to the digital read/write circuit cards to clock the RZ
U10 and transistors Q1 and Q2 form a gated head-
and deskew flip-flops. Waveform 9 (fig. 2-4) is the
current driver circuit. The transistors operate in a
RD CLK signal.
push-pull configuration to drive the center-tapped
j. Return to Zero (RZ). The RZ flip-flop (U3-A)
write head which is returned to a +5 vdc via switch
converts the NRZ1 format back to RZ format. This
Q4 on control logic circuit card assembly A4. Write
is accomplished by setting the RZ flip-flop with the
current is inhibited by the WR PERMIT SW
leading edge of the full-wave rectifier output
(waveform 7, fig. 2-4) and resetting it with the
command (para 2-8).
trailing edge of RD CLK as shown in waveform 10.
illustrates the amplified signals derived from the
k. Deskew. The deskew flip-flop (U3-B) converts
read head. The signal peaks indicate the point of
the RZ format to NRZ and deskews (desynchronizes)
magnetic flux reversal on the magnetic recording
the parallel digital data. All data stored in the RZ
tape. AR1 is an integrated linear amplifier with a
flip-flop in each of the data channels is syn-
gain of 200. Since the magnetic head signals are
chronously shifted by the trailing edge of the RD
about 15 mv peak-to-peak at 22.5 ips, the output of
CLK signal. The synchronous parallel digital data
AR1 can be expected to be approximately three
appears as NRZ data (waveform 11, fig. 2-4).
volts peak-to-peak.
f. Differentiate and Amplify. Since the signal
peaks of the read waveform represent magnetic flux
two-microsecond STROBE pulse on the control
reversals on the tape, peak detection is required to
logic circuit card (A4), then gating STROBE with
reconstruct the data. This is accomplished by dif-
SEL CMD via the output gating circuit on digital
ferentiating and amplifying the output of the read
read/write circuit card (A3).
head preamplifier AR1. Series capacitator C9 and
m. Variable Threshold. When in search mode (45
ips tape speed), the read output data is inhibited by
resistor R10 differentiate the signal which is then
amplified by operational amplifier AR4-B.
imposing a higher triggering threshold on the zero-
Waveform 5 (fig. 2-4) illustrates the differentiated
crossing detectors. This is accomplished by raising
and amplified read head signal. Filtering of ex-
the RD RST line high at the noninverting input of
traneous high frequency noise is provided by two
voltage comparator AR6-C. Comparator AR6-C
filtering networks R19/C28 and R16/C21 (fig.
and diodes CR1, CR2 and CR3 also set the output of
all zero-crossing detectors to the same state when
the read mode is enabled. This is necessary to
AR6 in conjunction with positive feedback from R22
reconstruct the first bit after an IRG (Inter-Record
and R27 (fig. FO-2) functions as a zero-crossing
Gap).
detector (Schmitt trigger). Waveform 5 (fig. 2-4)
n. Output Gating. Read data and RD STROBE
illustrates the 0.8 volt peak-to-peak triggering
are gated out of the digital read/write circuit cards
level that is fed to the detector. Waveform 6
to the interface via inverters U7 and AND gates U6.
illustrates the squared output of the detector which
The output gates are enabled when SEL CMD goes
is, essentially, in NRZ1 format.
low, indicating that the tape transport has been
properly addressed.
crossing detector is applied to a full-wave rectifier
2-8. Control Logic Circuit Description
consisting of U1-A, U1-D, U2-B, C36, R33, R37
and CR4 (fig. FO-2). This circuit provides a
a. General. The control logic circuit card (A4)
positive-going pulse for every positive- or negative-
receives input/output commands and provides the
2-8
