TM 11-7440-232-12/NAVELEX 0967-LP-275-5010
(2) Input signals on the receive line are coupled to an input low pass filter by a matching transformer. The
filter output is amplified by the receive amplifier and then applied to the receive band pass filter which performs initial
shaping of the duobinary input waveform. Final shaping occurs in the low pass filter at the discriminator output. The
bandpass filter output is applied to the limiter through the adjustable equalizer. The limiter produces a square wave
output and applies this signal to the discriminator. The discriminator converts the input signal frequency to an 'analog dc
voltage which is proportional to the input frequency. For input frequencies of 1200, 1800, and 2400 Hz, the output
voltages are respectively 8, 9, and 10 volts.
(3) The level selectors in the decoder and error detector consists of two differential amplifiers which convert
the analog output of the discriminator to a square wave form that will activate the decoder. Both selectors are used for
duobinary operation in order to recognize the 3-level output of the discriminator. For binary or 1200-bps operation, the
bias level of one selector is shifted by an interconnection option so that the selector provides the correct duration output
pulses from a 2-level discriminator signal. The decoder combines the separate outputs of the two level selectors to
produce a regenerated data pattern that matches the pattern originally applied to the distant transmitter. This pattern is
retimed to reduce the affects of jitter that may be introduced into the transmission path.
(4) The received data is retimed by using the transitions to synchronize the receiver clock. The data pulses
are differentiated and a resulting short duration pulse is applied to the receiver clock for each data transition. The pulses
control a phase comparator in the receiver clock so that the clock oscillator locks to the average bit rate of the received
data. A memory circuit in the comparator maintains the oscillator at the correct frequency when no transitions are
received for several seconds, and also prevents short term variations in the received data rate from affecting the
oscillator frequency. The oscillator amplifier supplies a square wave signal to the decoder and error detector, and also to
the clock output amplifier.
(5) Retimed data is obtained by applying the decoder output pulses to the receiver clock signal. Because jitter
appears during the transitions of the received data signal, it is eliminated in the retimed output of the data period. The
retimed data is amplified by the data amplifier and used in the associated receiving data processor.
(6) The line frequencies for duobinary operation follow a predictable pattern which is useful for detecting errors
at the receive terminal. The error detector counts "0" bits and compares the levels of "1" bits. Timing is provided by the
digital receiver clock. An error occurs if the same level selector produces an output for two "1" bits that are separated by
an odd number of "0" bits, or if different level selectors produce outputs for two "1" bits that are separated by an even
number of "0" bits.
(7) The error detector carrier alarm monitors the received signal level and provides an alarm output signal if
this level drops 20 db or more below the nominal input of -30 dbm to the limiter. An output amplifier in this circuit
supplies an alarm to the data carrier alarm module and to equipment external to the digital data modem. This alarm
condition continues until the line carrier signal increases to the predetermined level above the alarm level. This
arrangement provides positive alarm action.